M07100 - SEMI M71 - Specification for Silicon-on-Insulator (SOI) Wafers for CMOS LSI StdPbc-1113 This Test Method defines an

This Test Method defines an evaluation method for EFFU which is installed inside an enclosed space to remove particles that are generated inside process equipment

SEMI G69-0996 (Reapproved 0318)

using a differential mobility analyzer (DMA)

It may be applied to subsystems of other multi-resource equipment

so the die strength data is critical for the die quality and certification

M07100 - SEMI M71 - Specification for Silicon-on-Insulator (SOI) Wafers for CMOS LSI StdPbc-1113 This Test Method defines an1 Purpose 1. 1 This Specification defines thin layer silicon on insulator (SOI) wafer requirements for CMOS large scale integrated circuit (LSI) devices. In the case of 200 and 300 mm wafers this Specification is targeted for nodes from 130 to 14 nm. In the case of 150 mm wafers, older LSI generations are included as well. By defining parameters, inspection procedures and acceptance criteria, both suppliers and customers may uniformly define product